Bus-Switch Coding, for Dynamic Power Management in off-chip communication channels

The dynamic power management (DPM) represents an important challenge for extending the battery lifetime in a portable system. The power management, based on static and off-line approaches, does not consider the basic property of a modern battery, which recovers a fraction of its charge during the idle time. The DPM approach profiles a complex system in different power figures depending on a reduced set of macro-states. The DPM problem gives a sequence of macro-states which increases the battery lifetime. The dynamic power management is also required in complex systems where the power dissipation in communication channels represent a dominant factor. The modern communication arrangements operate at rate of some G Bit/sec, which implicated high transition activities, responsible of the dynamic power consumption. Moreover, the signal level involved in the output pads has a quadratic contribution in the dynamic power. The problem of low-power bus encoding has been extensively tackled in the past. The basic approach minimizes the transition density, directly related to the lines switching activities, responsible of the load/unload of the parasitic capacities. The current literature on low-power bus encoding provides solutions, which do not guarantee a good activity saving increasing the bus lines; this issue represents a huge limitation in the modern communication channels, which require high transmission bandwidth. The paper introduced a novel low-power bus encoding approach, based on tentatively encoding, clustering and re-ordering the lines of a wide system data bus used in multi-processor scenario. The “Bus-Switch” mechanism, as novel bus encoding approach, drastically reduces the transition activity, preserving the required bandwidth for high data-rate communications. Since the optimal bus switch encoder complexity grows significantly decreasing the level of clustering, a sub-optimal approach requires power management policy in order to effectively control the battery life. The paperwork presents an overview of the bus-switch mechanism, including the required architecture for encoding/decoding the input lines. The RTL-model has been translated in a modern technology library at 90nm low-leakage using the Synopsys Tool for placement and CTS